I. Field of the Disclosure
The technology of the disclosure relates generally to a processor-based system employing multiple voltage domains.
II. Background
Circuits are increasingly being designed with power conservation in mind. This is particularly the case for portable electronic devices that are battery-powered. Common examples include mobile phones and laptop computers, among others. Increased power consumption undesirably results in faster battery drainage and shorter battery life. One method of conserving power is to lower an operating frequency of the circuit according to the active power equation P=CV2f. However, reducing the operating frequency results in lower circuit performance (i.e., speed). Another method of conserving power is to lower the operating voltage, since generally, active power reduces quadratically for a given reduction in operating voltage. However, lowering the operating voltage in a circuit lowers speed performance, which may also be undesirable. Further, certain cells or components of a circuit may have a minimum operating voltage below which they will not operate to read and write data, as well as retain data.
To address the tradeoff between performance and power consumption, multiple operating voltage domains (“voltage domains”) are increasingly being provided in circuits. Circuit paths are provided which pass through the multiple voltage domains to provide different operating voltages to different components of a circuit. Providing multiple voltage domains allows a lower voltage domain to provide power to components that do not require minimum voltage levels to conserve power. Components that either have a minimum operating voltage for memory operation functionality or provide critical paths where performance cannot be sacrificed may be powered by the higher voltage domain. Providing multiple voltage domains also allows the lower voltage domain to be scaled-down to conserve power during a power conservation mode, or scaled-up to provide for increased performance (i.e., hyper-performance), without affecting the operation of the components in the higher voltage domain.
In this regard, FIG. 1 is a block diagram of an exemplary processor-based system 100. A logic power rail 102L and a memory power rail 102M are provided in the processor-based system 100. The logic power rail 102L is provided to provide logic power 104 from a logic power supply to logic blocks 106(1)-106(M) in a logic domain 108 in the processor-based system 100, where ‘M’ represents any number of logic blocks 106 desired. The memory power rail 102M is provided to provide memory power 110 from a memory power supply to memory arrays 112(1)-112(N) in a memory domain 114, where ‘N’ represents any number of memory arrays 112 desired. Power switches 116(1)-116(M) may be provided to control coupling the respective logic blocks 106(1)-106(M) to the logic power rail 102L. Power switches 118(1)-118(N) may also be provided to control coupling the respective memory arrays 112(1)-112(N) to the memory power rail 102M. Separate logic and memory power rails 102L, 102M are provided to provide two (2) separate voltage domains in the processor-based system 100, because it may be desired to scale down (i.e., lower) and/or collapse the voltage of the logic power rail 102L during lower power modes. If the memory arrays 112(1)-112(N) were powered through the logic power rail 102L, the logic power rail 102L could only be lowered in voltage to a minimum operating voltage needed for memory retention in the memory arrays 112(1)-112(N). The minimum operating voltage for memory arrays is conventionally higher than for logic circuits.
However, by providing the separate logic power rail 102L and memory power rail 102M in the processor-based system 100 in FIG. 1, the intrinsic decoupling capacitance present in the memory arrays 112(1)-112(N) is not coupled to the logic power rail 102L. Thus, additional intentional decoupling capacitance may need to be added to the logic blocks 106(1)-106(M) at the expense of area and leakage power, to mitigate or avoid voltage droops from occurring on the logic power rail 102L caused by transient current draw events by the logic blocks 106(1)-106(M).